FIG. 13 is an example of a conventional receiver device for single-carrier transmission using frequency-domain equalization (FDE). This receiver device includes receiving units 101-1 to 101-R, timing detectors 102-1 to 102-R, frequency offset compensating units 103-1 to 103-R, serial-to-parallel converters 104-1 to 104-R, fast Fourier transform (FFT) computation units 105-1 to 105-R, equalizers 106-1 to 106-R, weight operation units 107-1 to 107-R, a signal synthesizer 108, an inverse fast Fourier transform (IFFT) operation unit 109, a parallel-to-serial converter 110, a demodulator 111, and a local oscillator 112. Here, R represents a number of import ports.
In this single-carrier receiver device, received single-carrier signals supplied from R-pieces of communication ports of the receiver are converted using an oscillating signal from the local oscillator 112 to base-band digital signals in the receiving units 101-1 to 101-R.
By using a preamble signal for each port, the timing detectors 102-1 to 102-R detect signal positions and timings of the signals converted in the receiving units 101-1 to 101-R.
The frequency offset compensating units 103-1 to 103-R use preamble signals contained in the received single-carrier signals to estimate the frequency offset of the signals that were timing-detected by the timing detectors 102-1 to 102-R, and compensate them based on this estimated frequency offset.
The preamble signals are then supplied to the weight operation units 107-1 to 107-R, which calculate their equalization weights.
The serial-to-parallel converters 104-1 to 104-R execute a serial-to-parallel conversion of the data signal, and the FFT operation units 105-1 to 105-R then perform an FFT operation to obtain a frequency component of the received signal. The equalizers 106-1 to 106-R use weights calculated by the weight operation units 107-1 to 107-R to equalize the received signal in the frequency domain.
Thereafter, the signal synthesizer 108 synthesizes the frequency components, namely the signals of the ports, and the IFFT operation unit 109 executes an IFFT operation to convert this signal to a time signal. The signal that was converted to a time signal is subjected to a parallel-to-serial conversion by the parallel-to-serial converter 110, and is then modulated in the demodulator 111. Thus the single-carrier receiver obtains a transmitted data sequence.
FIG. 14 shows the configuration of a frequency offset compensating unit 103-r at port number r (=1 to R). The frequency offset compensating unit 103-r includes an offset estimating unit 1031-r and an offset compensating unit 1032-r. The offset estimating unit 1031-r uses a preamble signal contained in a received single-carrier signal from a corresponding timing detector 102-r (=1 to R) to calculate a frequency offset estimated value, and outputs the calculated frequency offset estimated value to the offset compensating unit 1032-r. 
The offset compensating unit 1032-r uses the offset estimated value calculated by the offset estimating unit 1031-r to compensate the offset of the received data signal contained in a received single-carrier signal from a corresponding timing detector 102-r (=1 to R), and outputs the result to a corresponding serial-to-parallel converter 104-r (=1 to R).
Non-Patent Document 1, below, describes conventional technology relating to the single-carrier receiver shown in FIG. 13.    [Non-Patent Document 1]: A. Gusmao, R. Dinis, and N. Esteves, “On frequency-domain equalization and diversity combining for broadband wireless communications,” IEEE Trans. Commun., vol. 51, no. 7, PP. 1029-1033, July 2003.